#Logi capture delay how to#

You will likely need more control over when to arm/enable the delay, and possibly control over how many seconds to delay (i.e.seconds_delay_done pulses for one I_CLK cycle when the delay has completed.NUM_SECONDS_TO_DELAY is some number of seconds you want to delay.counter_1sec_en pulses once every second, for a single I_CLK cycle.COUNTS_IN_1_SEC is a constant that is your clock frequency in Hz.Everything is synchronous to your clock, I_CLK.Here is a snippet of an example, to give you the idea: timebase : process (I_CLK) is To create a realtime delay of 10 seconds, you simply need to count 10 pulses of the seconds timebase enable. That enable is your 'seconds' timebase.Īll your other logic can be referenced to the 'seconds' timebase enable. Every time your counter reaches 0 (or 25e6, or any other single value in the count), you can pulse an enable for one clock cycle. That means you need to count up to 25e6 (or (25e6)-1, depending how you set it up), reset the counter back to zero, and begin counting again. That means there are 25e6 clocks in a second.

#Logi capture delay how to#

So you need to figure out how to convert from the period (duration) of a single clock to a second. Equating a real time delay in a synchronous design (any design with a clock) is as simple as counting clocks, or counting enables of a time base generated by counting clocks.įor example, say the smallest unit of real time you need to deal with is 1 second (that is, you will never need to deal with tenths, milliseconds, etc).